Instructions are 32 bits (4 bytes, 1 word) in length and must be stored at word-aligned memory locations. Instructions for the RV64 and RV128 variants are still 32 bits long.
RISC-V is a “three address” architecture. The ADD instruction looks like this:
```
ADD x4,x5,x7 # x4 = x5 + x7
```
Note that in the RISC-V assembly language, the destination is typically the leftmost operand.
Here are the instruction formats:
Type | Operands | Example
----- | ----- | -----
R-type instruction | RegD,Reg1,Reg2 | ADD x4,x6,x8 # x4 = x6+x8
I-type instruction | RegD,Reg1,Immed-12 | ADDI x4,x6,123 # x4 = x6+123<br>LW x4,8(x6) # x4 = Mem[8+x6]
S-type instruction | Reg1,Reg2,Immed-12 | SW x4,8(x6) # Mem[8+r6] = x4 (word)
B-type instruction (a variant of S-type) | Reg1,Reg2,Immed-12 | blt x4,x6,loop # if x4<x6, goto offset(pc)
U-type instruction | RegD,Immed-20 | LUI x4,0x12AB7 # x4 = value<<12<br>AUIPC x4,0x12AB7 # x4 = (value<<12) + pc
J-type instruction (a variant of U-type) | RegD,Immed-20 | jal x4,foo # call: pc=offset+pc; x4=ret addr
Here are the instruction encoding:
Type | Operands | Encoding
----- | ----- | -----
R-type instruction | RegD,Reg1,Reg2 | XXXX XXX2 2222 1111 1XXX DDDD DXXX XXXX
I-type instruction | RegD,Reg1,Immed-12 | VVVV VVVV VVVV 1111 1XXX DDDD DXXX XXXX
S-type instruction | Reg1,Reg2,Immed-12 | VVVV VVV2 2222 1111 1XXX VVVV VXXX XXXX
B-type instruction (a variant of S-type) | Reg1,Reg2,Immed-12 | VVVV VVV2 2222 1111 1XXX VVVV VXXX XXXX
U-type instruction | RegD,Immed-20 | VVVV VVVV VVVV VVVV VVVV DDDD DXXX XXXX
J-type instruction (a variant of U-type) | RegD,Immed-20 | VVVV VVVV VVVV VVVV VVVV DDDD DXXX XXXX
DDDDD = RegD
11111 = Reg1
22222 = Reg2
VVVVV = Immediate value
XXXXX = Op-code / function code