* Load Byte (Signed)
* General Form: LB RegD,Immed-12(Reg1)
* Example: LB x4,1234(x9) # x4 = Mem[x9+1234]
* Description: An 8-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1. The value is sign-extended to the full length of the register.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. There is no alignment issue and this instruction will execute atomically.
* Encoding: This is an I-type instruction.
* Load Byte (Unsigned)
* General Form: LBU RegD,Immed-12(Reg1)
* Example: LBU x4,1234(x9) # x4 = Mem[x9+1234]
* Description: An 8-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1. The value is zero-extended to the full length of the register.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. There is no alignment issue and this instruction will execute atomically.
* Encoding: This is an I-type instruction.
* Load Halfword (Signed)
* General Form: LH RegD,Immed-12(Reg1)
* Example: LH x4,1234(x9) # x4 = Mem[x9+1234]
* Description: A 16-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1. The value is sign-extended to the full length of the register.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. halfword-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Load Halfword (Unsigned)
* General Form: LHU RegD,Immed-12(Reg1)
* Example: LHU x4,1234(x9) # x4 = Mem[x9+1234]
* Description: A 16-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1. The value is zero-extended to the full length of the register.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1.The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Load Word (Signed)
* General Form: LW RegD,Immed-12(Reg1)
* Example: LW x4,1234(x9) # x4 = Mem[x9+1234]
* Description: A 32-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* RV64 / RV128: For a machine with a register width larger than 32-bits, the value is sign-extended to the full length of the register.
* Encoding: This is an I-type instruction.
* Load Word (Unsigned)
* General Form: LWU RegD,Immed-12(Reg1)
* Example: LWU x4,1234(x9) # x4 = Mem[x9+1234]
* Description: This instruction is only available for 64-bit and 128-bit machines. A 32-bit value is fetched from memory and moved into register RegD. The value is zero-extended to the full length of the register. The memory address is formed by adding the offset to the contents of Reg1. In a machine with 32-bit registers, neither sign-extension nor zero-extension is necessary for value that is already 32 bits wide. Therefore the “signed load” instruction (LW) does the same thing as the “unsigned load” instruction (LWU), making LWU redundant.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Load Doubleword (Signed)
* General Form: LD RegD,Immed-12(Reg1)
* Example: LD x4,1234(x9) # x4 = Mem[x9+1234
* Description: This instruction is only available for 64-bit and 128-bit machines. A 64-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1. Sign extension occurs for machines with 128-bit registers.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Load Doubleword (Unsigned)
* General Form: LDU RegD,Immed-12(Reg1)
* Example: LDU x4,1234(x9) # x4 = Mem[x9+1234]
* Description: This instruction is only available for 128-bit machines. A 64-bit value is fetched from memory and moved into register RegD. The value is zero-extended to 128-bits. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Load Quadword
* General Form: LQ RegD,Immed-12(Reg1)
* Example: LQ x4,1234(x9) # x4 = Mem[x9+1234]
* Description: This instruction is only available for 128-bit machines. A 128-bit value is fetched from memory and moved into register RegD. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an I-type instruction.
* Store Byte
* General Form: SB Reg2,Immed-12(Reg1)
* Example: SB x4,1234(x9) # Mem[x9+1234] = x4
* Description: An 8-bit value is copied from register Reg2 to memory. The upper (more signi2icant) bits in Reg2 are ignored. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. There is no alignment issue and this instruction will execute atomically.
* Encoding: This is an S-type instruction.
* Store Halfword
* General Form: SH Reg2,Immed-12(Reg1)
* Example: SH x4,1234(x9) # Mem[x9+1234] = x4
* Description: A 16-bit value is copied from register Reg2 to memory. The upper (more signi2icant) bits in Reg2 are ignored. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. halfword-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an S-type instruction.
* Store Word
* General Form: SW Reg2,Immed-12(Reg1)
* Example: SW x4,1234(x9) # Mem[x9+1234] = x4
* Description: A 32-bit value is copied from register Reg2 to memory. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* RV64 / RV128: For a machine with a register width larger than 32-bits, the upper bits of the register are ignored.
* Encoding: This is an S-type instruction.
* Store Doubleword
* General Form: SD Reg2,Immed-12(Reg1)
* Example: SD x4,1234(x9) # Mem[x9+1234] = x4
* Description: This instruction is only available in 64-bit and 128-bit machines. A 64-bit value is copied from register Reg2 to memory. The memory address is formed by adding the offset to the contents of Reg1. For a 128-bit machine the upper bits of the register are ignored.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. doubleword-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an S-type instruction.
* Store Quadword
* General Form: SQ Reg2,Immed-12(Reg1)
* Example: SQ x4,1234(x9) # Mem[x9+1234] = x4
* Description: This instruction is only available in 128-bit machines. A 128-bit value is copied from register Reg2 to memory. The memory address is formed by adding the offset to the contents of Reg1.
* Comment: The target location given by the 12-bit offset must be within the range of -2,048 .. 2,047 relative to the value in Reg1. The address of the memory location is not required to be properly aligned (i.e. word-aligned), but it is assumed that this instruction will execute faster with properly aligned addresses. This instruction is guaranteed to execute atomically if the address is properly aligned. If the address is not aligned, there is no guarantee of atomic operation.
* Encoding: This is an S-type instruction.