* Nop
* General Form: NOP
* Example: NOP # Do nothing
* Description: This instruction has no effect.
* Comment: There are several ways to encode the “nop” operation. Using ADDI is the canonical, recommended way. Also note that instructions with the bit encoding of 0x00000000 and 0xFFFFFFFF are specifically not used for “nop”. These two values are commonly returned from memory units when the actual memory is missing (i.e., unpopulated). The two values 0x00000000 and 0xFFFFFFFF are specified as “illegal instructions” and will cause an “illegal instruction exception” if fetched and executed.
* Encoding: This is a special case of a more general instruction. This instruction is assembled identically to: ADDI x0,x0,0
* Move (Register to Register)
* General Form: MV RegD,Reg1
* Example: MV x4,x9 # x4 = x9
* Description: The contents of Reg1 is copied into RegD.
* Encoding:This is a special case of a more general instruction. This instruction is assembled identically to: ADDI RegD,Reg1,0
* Load Upper Immediate
* General Form: LUI RegD,Immed-20
* Example: LUI x4,0x12345 # x4 = 0x12345<<12 (0x12345000)
* Description: The instruction contains a 20-bit immediate value. This value is placed in the leftmost (i.e., upper, most signi2icant) 20 bits of the register RegD and the rightmost (i.e., lower, least signi2icant) 12-bits are set to zero.
* RV64 / RV128: The description above applies to 32-bit machines. Regardless of register size, the immediate value is moved into bits 31:12. In the case of 64-bit registers or 128-bit registers, the value is sign-extended to 2ill the upper 32 or 96 bits (i.e., bits 63:32 or bits 127:32).
* Comment: This instruction is often used directly before an instruction containing a 12-bit immediate value, which will be added in to RegD. Together, they are used to effectively make a 32-bit value. In the case of 64-bit or 128-bit machines, this will be a 32-bit signed value, in the range -2,147,483,648 .. 2,147,483,647 (i.e., -231 .. 231-1).
* Encoding: This is a U-type instruction.
* load Immediate
* General Form: LI RegD,Immed-32
* Example: LI x4,123 # x4 = 0x0000007B
* Description: The immediate value (which can be any 32-bit value) is copied into RegD.
* Encoding: This is a special case of more general instructions and is assembled differently depending on the actual value present. If the immediate value is in the range of -2,048 .. +2,047, then it can be assembled identically to: ADDI RegD,x0,Immed If the immediate value is not within the range of -2,048 .. +2,047 but is within the range of a 32-bit number (i.e., -2,147,483,648 .. +2,147,483,647) then it can be assembled using this two-instruction sequence: LUI RegD,Upper-20ADDI RegD,RegD,Lower-12 where “Upper-20” represents the uppermost 20 bits of the value and“Lower-12” represents the least signi2icant 12-bits of the value.
* Add Upper Immediate to PC
* General Form: AUIPC RegD,Immed-20Example: AUIPC x4,0x12345 # x4 = PC + (0x12345<<12)
* Description: The instruction contains a 20-bit immediate value. This value is moved into the leftmost (i.e., upper, most signi2icant) 20 bits of and the rightmost (i.e., lower, least signi2icant) 12-bits are set to zero. The number so created is then added to the contents of the Program Counter. The result is placed in RegD. The value of the PC used here is the address of the instruction that follows the AUIPC.
* RV64 / RV128: The description above applies to 32-bit machines. In the case of 64-bit or 128-bits registers, the immediate value is sign-extended before being added to the PC. The size of the PC equal to the size of the registers.
* Comment: This instruction is often used directly before an instruction containing a 12-bit immediate value, which will be added in to RegD. Together, they are used to effectively make a 32-bit PC-relative offset. This is adequate to address any location in a 32-bit (4 GiByte) address space. In the case of 64-bit or 128-bit machines, this will be a 32-bit signed offset, in the range -2,147,483,648 .. 2,147,483,647 (i.e., -231 .. 231-1). If the address space is larger than 4 GiBytes, this technique will fail; a different instruction sequence is required. The current PC can be obtained by using this instruction with an immediate value of zero. Use of JAL to determine the current PC is not recommended.
* Encoding: This is a U-type instruction.
* Load Address
* General Form: LA RegD,AddressExample: LA x4,MyVar # x4 = &MyVar
* Description: The address of some memory location is copied into RegD. No access to memory occurs.
* Encoding: There is no actual “load address” instruction; instead the assembler substitutes a sequence of two instructions to achieve the same effect. The “address” can refer to any location within the 32-bit memory space. The address is converted to a PC-relative address, with an offset of 32 bits. This offset is then broken into two pieces: a 20-bit piece and a 12-bit piece. The instruction is assembled using these two instructions: AUIPC RegD,Upper-20ADDI RegD,RegD,Lower-12
* Set If Less Than (Signed)
* General Form: SLT RegD,Reg1,Reg2Example: SLT x4,x9,x13 # x4 = (x9<x13) ? 1 : 0
* Description: The contents of Reg1 is compared to the contents of Reg2 using signed comparison. If the value in Reg1 is less than the value in Reg2, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is an R-type instruction.
* Set Less Than Immediate (Signed)
* General Form: SLTI RegD,Reg1,Immed-12
* Example: SLTI x4,x9,123 # x4 = (x9<0x0000007B) ? 1 : 0
* Description: The immediate value (a sign-extended 12-bit value, i.e., -2,048 .. +2,047) is compared to the contents of Reg1 using signed comparison. If the value in Reg1 is less than the immediate value, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is an I-type instruction.
* Set If Greater Than (Signed)
* General Form: SGT RegD,Reg1,Reg2
* Example: SGT x4,x9,x13 # x4 = (x9>x13) ? 1 : 0
* Description: The contents of Reg1 is compared to the contents of Reg2 using signed comparison. If the value in Reg1 is greater than the value in Reg2, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is a special case of a different instruction. This instruction is assembled identically to: SLT RegD,Reg2,Reg1 # Note: regs are switched
* Set If Less Than (Unsigned)
* General Form: SLTU RegD,Reg1,Reg2Example: SLTU x4,x9,x13 # x4 = (x9<x13) ? 1 : 0
* Description: The contents of Reg1 is compared to the contents of Reg2 using unsigned comparison. If the value in Reg1 is less than the value in Reg2, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is an R-type instruction.
* Set Less Than Immediate (Unsigned)
* General Form: SLTIU RegD,Reg1,Immed-12
* Example: SLTIU x4,x9,123 # x4 = (x9<0x0000007B) ? 1 : 0
* Description: The immediate value (a sign-extended 12-bit value, i.e., -2,048 .. +2,047) is compared to the contents of Reg1 using unsigned comparison. If the value in Reg1 is less than the immediate value, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is an I-type instruction.
* Set If Greater Than (Unsigned)
* General Form: SGTU RegD,Reg1,Reg2
* Example: SGTU x4,x9,x13 # x4 = (x9>x13) ? 1 : 0
* Description: The contents of Reg1 is compared to the contents of Reg2 using unsigned comparison. If the value in Reg1 is greater than the value in Reg2, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is a special case of a different instruction. This instruction is assembled identically to: SLTU RegD,Reg2,Reg1 # Note: regs are switched
* Set If Equal To Zero
* General Form: SEQZ RegD,Reg1
* Example: SEQZ x4,x9 # x4 = (x9==0) ? 1 : 0
* Description: If the value in Reg1 is zero, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Comment: This instruction is implemented with an unsigned comparison against 1. Using unsigned numbers, the only value less than 1 is 0. Therefore if the less-than condition holds, the value in Reg1 must be 0.
* Encoding: This is a special case of a more general instruction. This instruction is assembled identically to: SLTIU RegD,Reg1,1
* Set If Not Equal To Zero
* General Form: SNEZ RegD,Reg2
* Example: SNEZ x4,x9 # x4 = (x9≠0) ? 1 : 0
* Description: If the value in Reg2 is not zero, the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Comment: This instruction is implemented with an unsigned comparison against 0. Using unsigned numbers, the only value not less than 0 is 0. Therefore if the less-than condition holds, the value in Reg2 must be not be 0.
* Encoding: This is a special case of a more general instruction. This instruction is assembled identically to: SLTU RegD,x0,Reg2
* Set If Less Than Zero (signed)
* General Form: SLTZ RegD,Reg1
* Example: SLTZ x4,x9 # x4 = (x9<0) ? 1 : 0
* Description: If the value in Reg1 is less than zero (using signed arithmetic), the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Encoding: This is a special case of a more general instruction. This instruction is assembled identically to: SLT RegD,Reg1,x0
* Set If Greater Than Zero (signed)
* General Form: SGTZ RegD,Reg2
* Example: SGTZ x4,x9 # x4 = (x9>0) ? 1 : 0
* Description: If the value in Reg2 is greater than zero (using signed arithmetic), the value 1 is stored in RegD. Otherwise, the value 0 is stored in RegD.
* Comment: “Reg2 > 0” is equivalent to “0 < Reg2”.
* Encoding: This is a special case of a more general instruction. This instruction is assembled identically to: SLT RegD,x0,Reg2