* Shift Left Logical Immediate
* General Form: SLLI RegD,Reg1,Immed-12
* Example: SLLI x4,x9,5 # x4 = x9<<5
* Description: The immediate value determines the number of bits to shift. The contents of Reg1 is shifted left that many bits and the result is placed in RegD. The shift value is not adjusted, i.e., 0 means no shifting is done. (Apparently all values, including 0, are allowed. ???)
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an I-type instruction.
* Shift Left Logical
* General Form: SLL RegD,Reg1,Reg2
* Example: SLL x4,x9,x13 # x4 = x9<<x13
* Description: Register Reg2 contains the shift amount. The contents of Reg1 is shifted left and the result is placed in RegD.
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an R-type instruction.
* Shift Right Logical Immediate
* General Form: SRLI RegD,Reg1,Immed-12
* Example: SRLI x4,x9,5 # x4 = x9>>5
* Description: The immediate value determines the number of bits to shift. The contents of Reg1 is shifted right that many bits and the result is placed in RegD. The shift is “logical”, i.e., zero bits are repeatedly shifted in on the most-signi2icant end.
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an I-type instruction.
* Shift Right Logical
* General Form: SRL RegD,Reg1,Reg2
* Example: SRL x4,x9,x13 # x4 = x9>>x13
* Description: Register Reg2 contains the shift amount. The contents of Reg1 is shifted right and the result is placed in RegD. The shift is “logical”, i.e., zero bits are repeatedly shifted in on the most-signi2icant end.
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an R-type instruction.
* Shift Right Arithmetic Immediate
* General Form: SRAI RegD,Reg1,Immed-12
* Example: SRAI x4,x9,5 # x4 = x9>>>5
* Description: The immediate value determines the number of bits to shift. The contents of Reg1 is shifted right that many bits and the result is placed in RegD. The shift is “arithmetic”, i.e., the sign bit is repeatedly shifted in on the most-signi2icant end.
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an I-type instruction.
* Shift Right Arithmetic
* General Form: SRA RegD,Reg1,Reg2
* Example: SRA x4,x9,x13 # x4 = x9>>>x13
* Description: Register Reg2 contains the shift amount. The contents of Reg1 is shifted right and the result is placed in RegD. The shift is “arithmetic”, i.e., the sign bit is repeatedly shifted in on the most-signi2icant end.
* RV64 / RV128: For 32-bit machines, the shift amount must be within 0..31. For 64-bit machines, the shift amount must be within 0..63. For 128-bit machines, the shift amount must be within 0..127.
* Encoding: This is an R-type instruction.
* Shift Instructions for RV64 and RV128
* SLLIW RegD,Reg1,Immed-12 # RV64 and RV128 only
* SLLW RegD,Reg1,Reg2 # RV64 and RV128 only
* SRLIW RegD,Reg1,Immed-12 # RV64 and RV128 only
* SRLW RegD,Reg1,Reg2 # RV64 and RV128 only
* SRAIW RegD,Reg1,Immed-12 # RV64 and RV128 only
* SRAW RegD,Reg1,Reg2 # RV64 and RV128 only
* SLLID RegD,Reg1,Immed-12 # RV128 only
* SLLD RegD,Reg1,Reg2 # RV128 only
* SRLID RegD,Reg1,Immed-12 # RV128 only
* SRLD RegD,Reg1,Reg2 # RV128 only
* SRAID RegD,Reg1,Immed-12 # RV128 only
* SRAD RegD,Reg1,Reg2 # RV128 only